LAS VEGAS, May 9, 2011 /PRNewswire/ -- INTEROP -- Xilinx, Inc. (Nasdaq: XLNX) today announced a major expansion of its communications portfolio to accelerate the industry's implementation of new packet processing, switching, and traffic management solutions for meeting the exponential growth in demand for high-bandwidth and feature-reach quality of service (QoS). The expansion includes the acquisition of Modelware, a leading provider of traffic management/packet processing silicon intellectual property (IP) cores and reference designs that simplify system development and enable greater differentiation for networking applications supporting 10G, 40G, 100G and beyond. Along with the expansion, Xilinx is introducing the industry's first Field Programmable Gate Array (FPGA)-based 100G traffic management reference design to help customers speed their evaluation and implementation of high bandwidth packet processing applications.
"By delivering a highly integrated solution encompassing packet processing/traffic management and an array of connectivity IP cores, together with their reference design, Xilinx is addressing the critical time to market and total cost of ownership requirements of equipment makers gearing up for the high bandwidth-granular services roll-outs underway by service providers, enterprise and data center operators," said Matthias Machowinski of Infonetics Research.
"By augmenting FPGAs that are already fine-tuned for high-bandwidth communications technology with Modelware's traffic management/packet processing portfolio, Xilinx will be extending and accelerating its ability to deliver the benefits of industry-leading programmable platforms to our large base of wired communications customers," said Krishna Rangasayee Corporate Vice President & General Manager, Xilinx Communications Business Unit. "Essentially, we are providing customers with a one stop shop that can help them address high bandwidth challenges, million-connection-network needs, and enable system capabilities that satisfy evolving demands for Quality of Service."
The Modelware acquisition strengthens Xilinx's ability to deliver FPGA-optimized packet processing, switching, and traffic management solutions that address very granular (trending to 1+ million queues) per-flow bandwidth provisioning as well as scalable high-bandwidth traffic aggregation capabilities (20G to 100G and beyond) across the service provider, enterprise networking and data center markets. Today, Modelware has the only FPGA-based IP capable of scaling to up to 100G + and running traffic rates at 150 million packets-per-second with 64B packet size on a single FPGA.
Traditionally, ASSP and network processor vendors have addressed the communications industry's challenges by either overbuilding their silicon with multiple sets of features, or adding post deployment software upgrade services, which in either case can lead to hidden costs. Over the past two to three years, service providers and system operators have been looking for "hitless" in-system upgrades and OEM vendors have turned to programmable logic to build systems that can scale, be flexible, field upgradable, customized to specific needs and offer lower total cost of ownership.
Modelware's solutions consists of very scalable, highly optimized IP cores purposefully tuned for Xilinx® FPGAs and deployed across the spectrum of packet processing, switching, and traffic management systems. Today, customers can build 100G traffic management systems based around the Virtex-6 HXT FPGAs now in production, which offer industry-leading serial bandwidth through a combination of 6.6 Gbps GTX transceivers and 11.18 Gbps GTH transceivers. As system architects look in their next generation systems to reach higher bandwidth – as well as expand the number of hierarchies, increase the number of flows and relevant per-flow policing, marking and shaping controls, on top of expanding the total number of high bandwidth ports – Xilinx's unified FPGA architecture offers a wider range of choices via migration to its 28nm 7-series FPGA families. Kintex-7 and Virtex-7 FPGAs support a wide array of memory controllers and high memory bandwidth to address the most demanding packet processing and traffic management configurations. Enabling the highest port density of any FPGA in its class, the Kintex-7 FPGA family supports up to 32, 12.5 Gbps transceivers while the Virtex-7 HT FPGA family offers up to 72, 13.1 Gbps , in combination with up to 16 , 28 Gbps transceivers.
The Modelware technology also encompasses several legacy cores such as HDLC, ATM, PWE3, which Xilinx will continue to use in order to support legacy installations such as the mobile backhaul space, and help customers with maintaining existing deployments and offer an easy migration path from TDM to all-IP solutions without a need for new hardware.
Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.